1. Field of the Invention
This invention relates to the field of sense amplifiers used to sense differential voltages on bitlines for reading 0s and 1s in cells of SRAM arrays and amplifying the differential voltages for use by an output buffer to drive a capacitive load.
2. Prior Art
U.S. Pat. No. 4,658,160 teaches a common gate differential sense amplifier which does not require additional level shifting circuits, is not sensitive to process variations and is resistant to hot electron effects. The invention of this patent teaches the use of current mirror pairs of transistors as active loads and a balanced pair of differential amplifiers having a common gate. The differential amplifiers provide DC level shifting without the need for additional circuitry while the active current mirrors provide differential to single ended conversion of the input-output signal which is then passed through one of more gain stages to drive an output buffer. U.S. Pat. No. 4,888,503 is an improvement over the invention described in U.S. Pat. No. 4,658,160 which is less sensitive to input voltage and current variations and is substantially independent of voltage changes on the data lines. U.S Pat. No. 4,796,230 is directed to a decoder circuit which provides for fastest sensing of the signal current from a SRAM cell. The decoder circuit of this invention transfers the signal from the bit line pairs to the output line pairs while isolating the bit line capacitance from the output line capacitance to reduce the total capacitance which must be driven for transfer of information from the SRAM to the sense amplifier. The isolation of the bit line capacitance from the output line capacitance results in a decrease in the time required for transferring data from the SRAM to the sense amplifier.